1. Field of the Invention
The present invention relates to the field of the fabrication of semiconductor devices, and, more particularly, to an improved chip bond layout for chip carrier for flip chip bonding.
2. Description of the Related Art
As semiconductor manufacturers continue to scale down on-chip features, the need to contact those reduced size features becomes a more significant constraint. The scaled features enable increased functionality. For example, in general, the number of inputs and outputs (I/O count) of an integrated circuit may be increased while maintaining the die size or, on the other hand, the chip size may be reduced while maintaining the functionality (and the I/O count) of the original design for the integrated circuit. In both cases, however, the density of inputs and outputs (I/Os) is increased. For a conventional peripheral bond pad arrangement, the resulting bond pad pitch (the distance between the center of two adjacent bond pads) is accordingly reduced. Conventional wire bond technology provides a method to bond, by thermo-compression or by thermo-sonic-compression, a thin gold wire to a bond pad on the chip and to a bond pad on the carrier to form an electrical connection to the carrier for each input/output (I/O) of the chip. Wire bond technology may be employed with bond pad pitches down to 70 μm. Wire bonding, however, is a sequential process, so that the total bonding time increases and, hence, renders this bonding technology more and more ineffective, with increasing I/O counts. Furthermore, the curved wire bonds exhibit a high inductance so that wire bonds are, in general, not appropriate for high frequency applications, such as mobile telephones, wireless LANs, or state of the art microprocessors with high clock rates. Thus, primarily for electrical and/or economical reasons, wire bond technology is being replaced by the flip chip bond technology.
The flip chip technology requires an equal bump pitch on the chip and on the carrier to which the chip is to be bonded. The minimal bump pitch achievable on a carrier depends on the carrier material and on the corresponding available technology. As a chip carrier material, ceramics, polyimides or fiber-reinforced resins like FR4 may be employed. In large-scale production, FR4 is a widely used material for its economical benefits. Conventional FR4 printed circuit board (PCB) technologies are currently not capable of being reliably used with a bond pad pitch of less than 150 μm.
For flip chip bonding, solder bumps arranged according to the desired bump layout are formed on both the chip carrier and the chip to be bonded. Electro and electroless plating, evaporative techniques and stencil or screen-based printing technologies may be employed to deposit the solder bump material on the chip and on the carrier. A subsequent solder reflow brings the solder material into the required bump shape. In the bonding process, the bumps on the carrier and the corresponding bumps on the chip are disposed adjacent to each other by means of a flip chip bonder. In a heat treatment, the solder bumps on the chip and on the carrier are melted and the corresponding bumps form a single bond structure between the chip and the carrier. The chip may be released from the flip chip bonder when the solder is still in a liquid phase to achieve a certain self-alignment due to surface tension effects caused by the characteristics of the liquid solder. The remaining tiny gap between the chip and the carrier may be filled to reduce thermally-induced mechanical stress that may otherwise adversely affect the formed bond structure due to different thermal expansion coefficients of the materials of the chip and of the chip carrier.
Contrary to wire bonding, flip chip bonding is not restricted to the employment of peripheral bond pads. Consequently, semiconductor manufacturers arrange the bond pads in two or more rows disposed in the peripheral region of the chip area (peripheral array), or redistribute the peripheral bond pads over the entire chip area (area array) to allow for a higher bond pad pitch. The ratio of a single row peripheral pitch to the full area array pitch is independent of the chip size for square chips but exhibits a proportional relation to the square root of the number of I/Os. For example, for an I/O count of 100, the ratio of the peripheral pitch to the corresponding area array pitch is approximately 2.5, whereas, for an I/O count of 1600, the ratio increases to 10, i.e., in particular for high I/O counts, the area array redistribution of bump pads provides an effective manner to increase the required bond pad pitch. The sectional view of a system 100 depicted in FIG. 1 illustrates the technology according to a typical prior art technique. A chip 102 is flip chip bonded onto a carrier 106 by bonds 104. The I/Os of the chip 102 are routed out on the upper wiring layer 110 by means of conductive lines 108.
Disadvantageously, contrary to the peripheral arrangement, the area array bond pads are more difficult to route out on the chip carrier since the connection lines to inner bond pads are typically routed out in the clearances between the bond pads. For high I/O counts, the number of inner I/Os which are routed out is, in general, too high to route all inner I/Os out while still meeting the design rules of the employed board technology. In particular, for high power applications, it may be a challenging task to route out the power supply lines in accordance with the board design rules due to the typical high line width requirements required to meet the current density constraints. As a consequence, additional wiring layers have been integrated into the printed circuit board to route out the I/Os not routable on the upper wiring layer. Routing out on additional wiring layers, however, requires at least one via to connect each bump pad formed on the upper wiring layer. A via connecting two features on different wiring layers typically comprises a pad on each participating wiring layer and a hole drilled through the insulation layer between the wiring layers. The hole is subsequently filled by a conductive material to form a conductive connection between the pads. The pads extend beyond the diameter of the hole so that each via needs more free space as generally available in full area array layouts. Chip bond layouts need to be accordingly redesigned to allow for higher I/O counts. Currently available bond layouts, however, may suffer from a decreased number of routable I/Os.
In view of the above-mentioned problems, there exists a need for an improved bond layout for chip carrier for flip chip mounting.